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3. Functional Description
The DDR and DDR2 SDRAM controllers instantiate an encrypted control logic and a
clear-text datapath. You can replace the control logic with your own custom logic.
Block Description
Figure 3–1 shows a block diagram of the DDR & DDR2 SDRAM controller.
Figure 3–1. DDR & DDR2 SDRAM Controller Block Diagram
local_addr
(Note 1)
local_be
local_burstbegin
local_read_req
local_refresh_req
local_size
DDR SDRAM Controller
ddr_a
ddr_ba
local_wdata
local_write_req
local_init_done
local_rdata
local_rdata_valid
local_rdata_valid_in_n
local_ready
local_refresh_ack
local_wdata_req
Control
Logic
(Encrypted)
ddr_cas_n
ddr_cke
ddr_cs_n
ddr_odt (2)
ddr_ras_n
ddr_we_n
dqs_ref_clk
fedback_clock_out
stratix_dll_control
addrcmd_clk
capture_clk
clk
dqs_delay_ctrl[5:0]
dqsupdate
fedback_clock_in
postamble_clk
Data Path
Module
(Clear Text)
clk_to_sdram
clk_to_sdram_n
ddr_dq
ddr_dqs
ddr_dm
resynch_clk
resynch_
clk_edge_select
write_clk
Notes to Figure 3–1 :
(1) You can edit the ddr prefix on the SDRAM interfaces signals.
(2) DDR2 SDRAM controller only.
Control Logic
Bus commands control SDRAM devices using combinations of the ddr_ras_n ,
ddr_cas_n , and ddr_we_n signals. For example, on a clock cycle where all three
signals are high, the associated command is a no operation (NOP). A NOP command
is also indicated when the chip select signal is not asserted.
? March 2009
Altera Corporation
DDR and DDR2 SDRAM Controller Compiler User Guide
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